Transistors and other devices are connected together to form circuits, such as very large scale integrated circuits, ultra-large scale integrated circuits, memory, and other types of circuits. When the size of transistors, for example, is reduced and device compaction is increased, problems may arise concerning parasitic capacitance, off-state leakage, power consumption, and other characteristics of a device. Semiconductors on insulator (SOI) structures have been proposed in an attempt to overcome some of these problems. However, SOI structures generally have a high rate of defects, as it is difficult to produce thin, uniform semiconductor layers in fabrication. Defect problems in SOI structures include defects within a single wafer (e.g., the thickness of a wafer differs at various points on the wafer) and defects from wafer to wafer (e.g., an inconsistent mean silicon layer thickness among SOI wafers). As transistor devices are made smaller, channel length is generally reduced. Reduction in the channel length generally results in an increased device speed, as gate delay typically decreases. However, a number of side effects may arise when channel length is reduced. Such negative side effects may include, among others, increased off-state leakage current due to threshold voltage roll-off (e.g., short channel effects).
One way of increasing device speed is to use higher carrier mobility semiconductor materials to form the channel. Carrier mobility is generally a measure of the velocity at which carriers flow in a semiconductor material under an external unit electric field. In a transistor device, carrier mobility is a measure of the velocity at which carriers (e.g., electrons and holes) flow through or across a device channel in an inversion layer. For example, higher carrier mobility has been found in narrow bandgap materials that include germanium (Ge). Germanium has electron and hole mobility of about 3900 cm2/Vs and about 1900 cm2/Vs, respectively, which are higher than that of electron and hole mobility of silicon, which are 1500 cm2/Vs and 450 cm2/Vs, respectively.
However, disadvantageously, conventional methods of introducing strain in a non-planar transistor channel using recess etch/raised source/drain regions on free standing Si fins have proven difficult. In planar transistor structures, source/drain regions may be provided that have a crystalline material with lattice spacing larger than a lattice spacing of the channel, thus straining the channel. However, in the case of a non-planar transistor channel including a fin, the fin is free standing, and thus inducing the required amount of strain in the fin by virtue of engineering the source/drain region lattice spacing has proven difficult if not impossible.
Another structure for employing a narrow bandgap material for a non-planar transistor is to form one or more nanowires to serve as the channel region. Employing a nanowire as a channel of a transistor tends to yield a transistor having a low power consumption, a high integration degree, a rapid response speed, etc. The semiconductor nanowire indicates a wire having a width of several nanometers to scores of nanometers. However, the nano-technology for manufacturing the transistor has not yet been sufficiently developed. Thus, the formation, assembly and alignment of nanowires according to the prior art has proven difficult. According to the prior art, nanowires may be grown by way of CVD using catalytic nucleation sites for the nanowires. However, disadvantageously, growing nanowires as mentioned above results in nanowire structures that grow randomly, and that, as a result, tend to present random dimensions/placement.
The prior art fails to provide an effective and reliable method to form a strained or nanowire channel region adapted for use on a non-planar transistor.
For simplicity and clarity of illustration, elements in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Where considered appropriate, reference numerals have been repeated among the drawings to indicate corresponding or analogous elements.